1. Field of the Invention
This invention is related to the field of digital communications and, more particularly, to the transmission of digital signals.
2. Description of the Related Art
The design of advanced digital communication systems requires careful attention to the reliable transmission and receipt of signals in order to ensure proper functioning. One popular design methodology is that of synchronous design. Generally speaking, synchronous designs utilize a central clock which is distributed to various parts of the design. While utilizing a synchronous approach may simplify certain aspects of the design process, this approach is not without its problems. One such problem is that of clock skew. Because a central clock signal may be distributed to various parts of a system via board traces, backplanes, interconnects, and the like, clock skew may exceed that which can be tolerated by registers and other elements. Consequently, design techniques to minimize clock skew must be utilized to ensure proper system functioning. An additional consequence of using the synchronous design approach and distributing a clock signal throughout a system is the inherent phase delay that may accumulate. In a design where higher frequencies and performance are desired, these delays ultimately may cause the synchronous design approach untenable.
Source synchronous designs utilize a different approach than the synchronous design approach in order to obtain higher performance. Source synchronous designs transmit both a clock signal and data from a transmitter to receiver. The receiver then uses the received clock signal to recover the data. Because the clock signal and data are transmitted from the transmitter to receiver in parallel, some of the problems of a widely distributed clock signal are avoided. Consequently, higher frequencies may be more reliably maintained. Also, many source synchronous designs may utilize both edges of a transmitted clock signal for the transmission of data. In this manner, even higher data throughputs may be achieved. Further, because both the clock signal and data are transmitted by a particular source, longer trace lengths may be supported.
While source synchronous designs may provide certain advantages over synchronous designs, they are not without their own problems. For example, the design must account for clock jitter due to noise. In addition, certain systems may require transmitting signals over relatively long distances. Even with the greater lengths which may be achieved using source synchronous designs, jitter and other signal degradation may limit the effective length of a transmission line. Further, signal degradation may also reduce the effective operating frequency which can be achieved.
What is desired is a method and mechanism for improving signal transmitting signals in source synchronous designs.